1. Field of the Invention
It is related to semiconductor integrated circuits, and particularly relates to a voltage detecting circuit for detecting the level of a potential that needs to be monitored.
2. Description of the Related Art
Semiconductor integrated circuits such as DRAM may employ a boosted-voltage generating circuit for internally generating a boosted power supply potential and/or a negative-voltage generating circuit for generating a negative potential based on a power supply voltage having predetermined potentials supplied from an external source. In the case of DRAM, for example, a boosted-voltage generating circuit for supplying a boosted potential as a word-line activating potential higher than the HIGH level is used to reliably store the HIGH level in memory cells at high speed. Further, a negative voltage generated by a negative-voltage generating circuit is used in the memory cell array.
FIG. 1 is a drawing showing an example of the configuration of a DRAM including a boosted-voltage generating circuit and negative-voltage generating circuit. A DRAM 10 shown in FIG. 1 includes an internal power supply generating unit 11, a memory cell array 12, and a memory access control circuit 13. The memory access control circuit 13 performs a read and write operation with respect to the memory cell array 12 in response to control signals and address signals supplied from an external source. The internal power supply generating unit 11 includes a voltage detecting circuit 21 and a voltage generating circuit 22. The voltage generating circuit 22 includes a boosted-voltage generating circuit 23 and a negative-voltage generating circuit 24. A boosted potential and negative potential generated by the boosted-voltage generating circuit 23 and negative-voltage generating circuit 24 are supplied to the memory cell array 12. The memory cell array 12 includes a transistor 25, a capacitor 26, a word-line driver 27, a word line WL, and a bit line BL. A plurality of word lines and a plurality of bit lines are arranged in rows and columns. A transistor 25 and capacitor 26 connected to each intersecting point constitutes a memory cell for storing one bit.
The voltage detecting circuit 21 detects a boosted potential and negative potential supplied to the memory cell array 12. Specifically, the voltage detecting circuit 21 compares a potential generated by dividing the boosted potential with a reference potential, and drives the boosted-voltage generating circuit 23 to step up the output of the boosted-voltage generating circuit 23 upon detecting that the divided potential drops below the reference potential. Further, the voltage detecting circuit 21 compares a potential generated by dividing the negative potential with a reference potential, and drives the negative-voltage generating circuit 24 to lower the output of the negative-voltage generating circuit 24 upon detecting that the divided potential rises above the reference potential.
FIG. 2 is a drawing showing an example of the circuit configuration of the voltage detecting circuit 21. The circuit configuration shown in FIG. 2 corresponds to the portion of the voltage detecting circuit 21 that relates to the detection of a boosted potential.
The voltage detecting circuit 21 of FIG. 2 includes resistor elements R1 and R2, a high-frequency-compensation capacitive element C1, and a differential amplifier 31. The differential amplifier 31 operates as a comparator circuit for comparing two inputs, and has an output thereof supplied as a drive signal (activation signal) to the boosted-voltage generating circuit 23 so as to control the active/inactive state of the boosted-voltage generating circuit 23. The inverted input node of the differential amplifier 31 receives a potential obtained by the resistor elements R1 and R2 dividing a boosted potential output from the boosted-voltage generating circuit 23, and the non-inverted input of the differential amplifier 31 receives a reference potential generated by a reference potential generating circuit 29.
As the output potential of the boosted-voltage generating circuit 23 drops due to current consumption in the memory cell array 12, the above-noted divided potential becomes lower than the reference potential. In response to the divided potential lower than the reference potential, the differential amplifier 31 asserts the drive signal, which is its output signal. In response to the assertion of the drive signal, the boosted-voltage generating circuit 23 becomes active, thereby raising its output potential. As the divided potential becomes higher than the reference potential due to the rise of the output potential, the operation of the boosted-voltage generating circuit 23 comes to a halt.
In order to suppress needless current consumption, resistor elements having extremely large resistances are used as the resistor elements R1 and R2. The amount of an electric current that actually flows is around 1 microampere. The divided potential appearing at the joint point between the resistor elements R1 and R2 thus does not respond with sufficient speed to a change in the boosted potential. There is thus a problem in that the response characteristics at high frequencies are not satisfactory. The high-frequency-compensation capacitive element C1 is provided for the purpose of compensating for the response characteristics at high frequencies. The high-frequency-compensation capacitive element C1 provides a low-impedance coupling between the boosted potential and the divided potential at high frequencies, thereby achieving a configuration in which a high-frequency fluctuation in the boosted potential directly propagates to the divided potential. This attains satisfactory response characteristics at high frequencies.
FIG. 3 is a drawing showing an example of the circuit configuration of the voltage detecting circuit 21. The circuit configuration shown in FIG. 3 corresponds to the portion of the voltage detecting circuit 21 that relates to the detection of a negative potential.
The voltage detecting circuit 21 of FIG. 3 includes resistor elements R3 and R4, a high-frequency-compensation capacitive element C2, and a differential amplifier 32. The output of the differential amplifier 32 is supplied as a drive signal (activation signal) to the negative-voltage generating circuit 24 so as to control the active/inactive state of the negative-voltage generating circuit 24. The non-inverted input node of the differential amplifier 32 receives a potential obtained by the resistor elements R3 and R4 dividing a negative potential output from the negative-voltage generating circuit 24, and the inverted input of the differential amplifier 32 receives a reference potential generated by the reference potential generating circuit 29.
The operation of the voltage detecting circuit 21 shown in FIG. 3 is basically the same as that of the voltage detecting circuit 21 shown in FIG. 2. Like the high-frequency-compensation capacitive element C1 shown in FIG. 2, the high-frequency-compensation capacitive element C2 is provided for the purpose of compensating for response characteristics at high frequencies. The high-frequency-compensation capacitive element C2 provides a low-impedance coupling between the negative potential and the divided potential at high frequencies, thereby achieving a configuration in which a high-frequency fluctuation in the negative potential directly propagates to the divided potential. This attains satisfactory response characteristics at high frequencies.
In the configurations shown in FIG. 2 and FIG. 3, the resistor elements R1 through R4 may be implemented by use of a metal material or polysilicon material disposed in a metal layer or polysilicon layer. In recent years, however, the metal layer and polysilicon layer serving as signal interconnect layers have become low resistance for the purpose of increasing signal speed. Because of this, it is difficult to manufacture resistor elements having high resistance. If the resistor elements R1 through R4 are made by using N-type or P-type diffusion layers having high resistance, elements of relatively small size having desired resistance may be obtained.
The capacitive elements C1 and C2 may be implemented by placing an oxide film between a diffusion layer and a polysilicon layer or metal layer situated above the diffusion layer. Alternatively, a capacitor may be implemented by using an N-channel or P-channel MOS transistor.
FIGS. 4A and 4B are drawings showing an example of a capacitive element implemented by using a P-channel MOS transistor. FIG. 4A is a plan view of the capacitive element, and FIG. 4B is a cross-sectional view of the capacitive element.
The configuration shown in FIGS. 4A and 4B includes metal interconnects 41 disposed in a metal layer for connection to a generated power supply, a polysilicon gate 42, a gate contact 43, source-drain contacts 44, a P-type diffusion layer 45, an N-type substrate 46, and a metal interconnect 47 disposed in the metal layer for connection to a divided potential node. The metal interconnects 41 are coupled to the P-type diffusion layer 45 via the source-drain contacts 44, and the metal interconnect 47 is coupled to the polysilicon gate 42 via the gate contact 43. An oxide film is placed between the P-type diffusion layer 45 and the polysilicon gate 42, thereby forming a capacitor between the P-type diffusion layer 45 and the polysilicon gate 42.
A voltage detecting circuit having a similar configuration to that of the voltage detecting circuit 21 shown in FIG. 2 is used in various circuits. FIG. 5 is a drawing showing an example of the configuration of a DC-DC converter using a voltage detecting circuit.
A DC-DC converter 50 shown in FIG. 5 includes a voltage detecting circuit 51, switching-element-control circuits 52 and 53, transistors 54 and 55, an inductor 56, and a capacitor 57. The voltage detecting circuit 51 detects an output voltage VOut of the DC-DC converter 50. Specifically, the voltage detecting circuit 51 compares a potential generated by dividing the output potential with a reference potential, and makes the transistor 54 conductive to raise the output potential upon detecting that the divided potential drops below the reference potential. Further, the voltage detecting circuit 51 makes the transistor 55 conductive to lower the output potential upon detecting that the divided potential rises above the reference potential. The voltage detecting circuit 51 operating as described above may be implemented by using substantially the same circuit configuration as that of the voltage detecting circuit 21 shown in FIG. 21.
In a voltage detecting circuit used in a semiconductor integrated circuit as described above, a capacitive element may be implemented by placing an oxide film between a diffusion layer and a polysilicon layer or metal layer, or may be implemented by use of an N-channel or P-channel MOS transistor. Either configuration, however, has a problem in that the circuitry size of a capacitive element is so large as to hinder the effort of reducing circuit size.
Accordingly, there is a need for a voltage detecting circuit that does not use a capacitive element in a semiconductor integrated circuit.
[Patent Document 1] Japanese Patent Application Publication No. 5-63147
[Patent Document 2] Japanese Patent Application Publication No. 2001-237374